The present invention relates to a disk memory device which records and reproduces an optical, a magnetic or an optical-magnetic data by using a disk as a record medium, especially, to a signal processing device used to a data reproduction operation.
Conventionally, a disk memory device which optically, magnetically or optical-magnetically records and reproduces data on a disk (storage medium) has a read-out signal processing circuit to reproduce (decode) data (data recorded on the disk) from the read-out signal (read signal) read from the disk with a read head (including a read/write composite head). In the disk memory device, there are a magnetic disk drive which is called hard disk drive (HDD), an optical disk drive, and a magnetic-optical disk drive, specifically. The read-out signal processing circuit is often constructed specifically by an exclusive IC which integrally includes record and reproduction function as a read/write circuit.
The read-out signal processing circuit roughly comprises an amplifier which amplifies the read-out signal read from the head, a waveform equalizer to waveform-equalize the read-out signal waveform, a data detection circuit to perform a data detection processing (identification processing of binarization), and a decoder (decoding circuit) to decode to the record data.
The waveform equalizer is produced to correct the waveform distortion caused by the result of passing a record channel (system which consists of the record medium/the head) and make the detection error rate in the data detection processing within the permissive range when data is recorded on the disk. Conventionally, a linear equalization method of modeling the record channel to the linear system and correcting linear distortion of the read-out signal is adopted. Specifically, an adaptive digital filter to adaptively follow to the characteristic change of the record channel is often adopted.
Recently, the signal processing technology of the PRML (Partial Response Maximum Likelihood) method is being adopted as a data detection circuit. This PRML method is a method to sequentially detect data by using the correlation before and behind the read-out signal waveform, and, specifically, the Viterbi decoder is used.
In recent years, for example, a high record density like several Gbits/in2 has been achieved in HDD to make the memory capacity of the disk memory device mass. In such a high record density, since it is impossible to set a linear model to the binary data recorded on the disk in a response characteristics of the conventional record channel, it is necessary to consider a nonlinear element. Here, when the ratio of a nonlinear distortion becomes large, the equalization residual error increases in the linear equalization circuit, and securing the detection error rate within the permissive range becomes difficult in the data detection processing.
The waveform equalizer, which uses a hierarchical network or multilayer perceptron type neural network scheme (Hereafter, so called as a MLP type) is proposed as a method to equalize a nonlinear distortion of the read-out signal waveform. In the conventional read-out signal processing circuit, as for the read-out signal to which a nonlinear waveform distortion is removed by the MLP type waveform equalizer, the data detection processing is executed with the conventional data detection circuit.
As mentioned above, with a high recording density in the disk memory device, a nonlinear distortion component which is occupied to the distortion element included in the read-out signal waveform when data is reproduced from the disk, increases up to the extent which cannot be disregarded. Therefore, the necessity of the nonlinear waveform equalization processing to remove a nonlinear distortion component becomes large. It is known that it is effective to an equalization processing of a nonlinear distortion component in the waveform equalizer which uses the MLP type signal processing circuit.
By the way, a learning process of determining the weighting coefficient of the network is necessary for the equalization circuit of the neural network scheme. In this learning process, a calculation method called as a backpropagation algorithm is used. This method corrects a difference between an actual value on the output edge and the ideal value which is the equalization target according to the degree of contribution to the output (that is, a ratio which influences to the output) according to the weighting coefficient of the network. Since largeness of the equalization error of the output of the equalization circuit is directly related to the detection error rate in the data detection method to detect the data for each bit, the learning method by the backpropagation algorithm is reasonable.
However, it becomes difficult to control the detection error rate in the data detection method to detect the data for each bit in which the interference between adjacent bits of the read-out signal waveform is impermissible with a request of a high record density in recent years. In the signal processing method as above-mentioned PRML method, the amount of mutual interference between adjacent bits of the read-out signal waveform is permitted in some degree, and data detection processing is performed with following the state of the change of the waveform value by interference with the sequence. That is, in the signal processing method of the PRML method, since the power of the signal to extend between adjacent bits can be used valid by the permission of mutual interference of the read-out signal waveform, it becomes possible to lower the detection error rate to the read-out signal of same signal-to-noise ratio (S/N). In this case, it is general that the maximum likelihood sequence detector (ML decoder or Viterbi decoder) is designed on an assumption of the linear waveform interference to avoid the complication of the circuit. Therefore, the equalization circuit of the neural network scheme to assume the read-out signal waveform only of linear waveform interference according to the class of the PRML method to be a learning target is theoretically valid.
However, it is not practical to use the equalization circuit, which adjusts the equalization error with the learning target to 0, in the cost, when the neural network scheme is actually applied to the circuit. In addition, it is difficult to completely remove the influence of an individual device and a change with the lapse of time. Therefore, the following problems are occurred in this case, when the circuit design to which some equalization error is remained is performed. The lowest point of the detection error rate and the residual equalization error becomes a disagreement with the lowest point of the residual equalization error in the evaluation value at the learning process, when the ML decoder which does not consider the equalization error and the equalization circuits of the neural network scheme (MLP type equalization circuit) are combined. This reason is why the residual equalization error of the equalization circuit is becoming of colored noise with the correlation, but the ML decoder has a maximum performance when the deviation of ideal value is an additive white Gauss noise.
In other words, the equalization circuit of the neural network scheme using the learning method, to which the residual equalization error in the output is minimized, does not always operate as the error rate becomes lowest. It is ideal to perform the learning of the equalization circuit of the neural network scheme executed by using the output of an ML detector, when the read-out signal is equalized by the equalization circuit and the circuit to detect data with the ML detector (Viterbi decoder) is constructed. However, since the output of the ML detector is a result which includes the ML sequence detection operation, it is not practical to use the evaluation value to the learning process of the equalization circuit of the neural network scheme because of a lot of problems.
An object of the present invention is to provide a disk memory device of effectively lowering a data error rate and high capacity and high reliability, by learning a feature of an input signal string by using the signal processing circuit of the neural network scheme of the MLP type etc., and outputting the same value as the output when the conventional data detector is used together.
A disk memory device (optical disk drive) according to the present invention comprises: a head (an optical pickup) which reads a read-out signal from a disk; an amplifier which amplifies an analog signal waveform of the read-out signal read from the:head; a filter which decreases a noise of the read-out signal output from the amplifier; an A/D converter which converts the read-out signal of which noise is decreased by the filter into a digital signal including a waveform distortion component; and a neural network type signal processing circuit which detects a binarized data from the digital signal.
A first signal processing device of a disk read-out signal comprises a neural network type signal processing circuit which detects a binarized data from the digital signal including a waveform distortion component, and which comprises an input layer which has a plurality of delay elements which have a delay time of a data clock cycle and are connected in series, a hidden layer which has a plurality of nodes without a connection relationship mutually, and an output layer which has one output node, and wherein each of signals on each end of the delay elements which construct the input layer is multiplied by a coupling weighting value and a result thereof is input to each node in the hidden layer, each of the plurality of nodes included in the hidden layer outputs a value of a nonlinear function for a sum total of an input, the output node inputs a value by which a coupling weighting value is multiplied to an output of each of the plurality of nodes included in the hidden layer, respectively, and outputs an output value of a nonlinear function to an input sum total of the output node.
A second signal processing device of a disk read-out signal comprises a neural network type signal processing circuit which detects a binarized data from the digital signal including a waveform distortion component, and which comprises an input signal sampling layer in which an input signal waveform is sampled, a pattern recognition layer constructed with pattern recognition nodes which multiply an amplitude value of the sampled input signal waveform by a weighting coefficient obtained by a learning process, and an output value judgment node which multiplies an output value from each pattern recognition node in the pattern recognition layer by the weighting coefficient obtained by the learning process, judges xe2x80x9c0xe2x80x9d data or xe2x80x9c1xe2x80x9d data based on this each multiplication result, detects binarized data from the second read-out signal.
The preferred manner of the present invention is as follows.
(1) The neural network type signal processing circuit includes a multilayer perceptron type neural network.
(2) The neural network type signal processing circuit comprises an input layer which has a plurality of delay elements which have a delay time of a data clock cycle and are connected in series, a hidden layer which has a plurality of nodes without a connection relationship mutually, and an output layer which has one output node, each of signals on each end of the delay elements which construct the input layer is multiplied by a coupling weighting value and a result thereof is input to each node in the hidden layer, each of the plurality of nodes included in the hidden layer outputs a value of a nonlinear function for a sum total of an input, the output node inputs a value by which a coupling weighting value is multiplied to an output of each of the plurality of nodes included in the hidden layer, respectively, and outputs an output value of a nonlinear function to an input sum total of the output node.
(3) The nonlinear function is a sigmoid function.
(4) The signal processing circuit comprises an input signal sampling layer in which an input signal waveform is sampled, a pattern recognition layer constructed with pattern recognition nodes which multiply an amplitude value of the sampled input signal waveform by a weighting coefficient obtained by a learning process, and an output value judgment node which multiplies an output value from each pattern recognition node in the pattern recognition layer by the weighting coefficient obtained by the learning process, judges xe2x80x9c0xe2x80x9d data or xe2x80x9c1xe2x80x9d data based on this each multiplication result, detects binarized data from the second read-out signal.
For example, after performing the waveform equalization processing by the waveform equalizer, the conventional signal processing system detects data from the read-out signal with the data detection circuit such as the Viterbi decoder. In contrast to this, the present invention adopts the signal processing system which inputs the read-out signal to which the noise is removed with, for example, the low-pass filter to the MLP type signal processing circuit, directly detects the binary data (binarized data) from the corresponding read-out signal, and outputs it. In other words, the signal processing system according to the present invention studies the signal pattern which removes neither the waveform distortion component included in the read-out signal conventionally nor the noise component but includes them, and determines the weighting coefficient obtained from this learning process. And, the signal processing circuit which extracts the feature of the signal pattern by the weighting coefficient and detects binarized data corresponding to this feature.
Therefore, with the signal processing circuit of such a configuration, since the process by which the read-out signal which includes a nonlinear distortion is converted into a suitable waveform for a linear signal processing system once can be excluded, data can be detected from the read-out signal which includes a nonlinear component by an enough low detection error rate by improving the effect of learning in the neural network scheme.
According to the present invention, in the disk memory device such as, for example, an optical disk drive, since the presence of the data error can be directly studied for the read-out signal which has the nonlinear distortion component by including the data detection function to the signal processing circuit of the neural network scheme of the MLP type etc., it becomes possible to effectively lower the influence of the nonlinear distortion component. Therefore, it becomes possible to remove the influence of the nonlinear distortion component by developing the waveform equalization function of the neural network scheme to minimize the residual equalization error enough, to effectively lower the data detection error rate with this, and to provide the disk memory device of high capacity and high reliability.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.